Memory, and more specifically latency in accessing memory, continues to limit the performance of modern processors. One way to mitigate high memory latency is to use a cache memory hierarchy within a processor. Another technique to hide memory latency is to prefetch cache lines into this cache hierarchy. Typically, a prefetch request is handled prior to the arrival of an actual demand request. As a result, subsequent demand requests from a core may hit the prefetched cache line in the core caches.
However prefetching and replacement policies are not necessarily synergistic. Replacement policies are designed to retain cache lines that have low reuse distance, defined as the average time between consecutive accesses to the same cache line. However, inefficiencies of current cache replacement policies can still lead to delays in accessing data.